发明名称 |
Temporary self-aligned stop layer is applied on silicon sidewall |
摘要 |
A method is provided for forming NMOS and PMOS transistors with ultra shallow source/drain regions having high dopant concentrations. First sidewall spacers and nitride spacers are sequentially formed on the sides of a gate electrode followed by forming a self-aligned oxide etch stop layer. The nitride spacer is removed and an amorphous silicon layer is deposited. The etch stop layer enables a controlled etch of the amorphous silicon layer to form silicon sidewalls on the first sidewall spacers. Implant steps are followed by an RTA to activate shallow and deep S/D regions. The etch stop layer maintains a high dopant concentration in deep S/D regions. After the etch stop is removed and a titanium layer is deposited on the substrate, an RTA forms a titanium silicide layer on the gate electrode and an extended silicide layer over the silicon sidewalls and substrate which results in a low resistivity.
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申请公布号 |
US2005151203(A1) |
申请公布日期 |
2005.07.14 |
申请号 |
US20040754833 |
申请日期 |
2004.01.09 |
申请人 |
TAIWAN SEMICONDUCTOR MANUFACTURING CO. |
发明人 |
CHO SHU-YING;CHUNG CHIEN-MING;HUANG YUAN-CHANG |
分类号 |
H01L21/3213;H01L21/336;H01L21/8238;(IPC1-7):H01L21/823;H01L29/94 |
主分类号 |
H01L21/3213 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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