发明名称 Concatenated equalizer/trellis decoder architecture for an hdtv receiver
摘要 A concatenated equalizer/trellis decoding system for use in processing a High Definition Television signal. The re-encoded trellis decoder output, rather than the equalizer output, is used as an input to the feedback filter of the decision feedback equalizer. Hard or soft decision trellis decoding may be applied. In order to account for the latency associated with trellis decoding and the presence of twelve interleaved decoders, feedback from the trellis decoder to the equalizer is performed by replicating the trellis decoder and equalizer hardware in a module that can be cascaded in as many stages as needed to achieve the desired balance between complexity and performance. The present system offers an improvement of between 0.6 and 1.9 decibels. Cascading of two modules is usually sufficient to achieve most of the potential performance improvement.
申请公布号 US2005154967(A1) 申请公布日期 2005.07.14
申请号 US20040511401 申请日期 2004.10.14
申请人 HEO SEO W.;PARK JEONGSOON;GELFAND SAUL;MARKMAN IVONETE 发明人 HEO SEO W.;PARK JEONGSOON;GELFAND SAUL;MARKMAN IVONETE
分类号 H03M13/25;H03M13/41;H04B7/005;H04L1/00;H04L25/03;H04N5/00;H04N5/21;H04N5/44;(IPC1-7):H03M13/03 主分类号 H03M13/25
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