| 摘要 |
A semiconductor memory device is operable in a full capacity mode and at least one reduced capacity mode, and includes a memory array having a plurality of memory blocks, each of the memory blocks having at least one word line. An address generation circuit generates a first multi-bit address signal having a logic value which is sequentially incremented by one during each of successive refresh periods. An address sorting circuit receives the first multi-bit address signal and outputs a second multi-bit address signal in which one or more least significant bits of the first multi-bit address signal are arranged in the second multi-bit address signal to indicate a memory block of the memory array, and in which remaining bits of the first multi-bit address signal are arranged in the second multi-bit address to indicate a word line within the selected memory block. The word lines of the memory array are refreshed according to the second multi-bit address signal.
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