发明名称 INFORMATION PROCESSING SYSTEM
摘要 PROBLEM TO BE SOLVED: To provide a system where a plurality of dedicated computers 3 are connected through a bus 2 to a host computer 1 for easily executing the logical circuit configuration of a programmable gate array(FPGA) 5 set in a dedicated computer in a short period of time. SOLUTION: The dedicated computer 3 is provided with a bus interface 4 for acquiring information on a bus 2 corresponding to its own address space, an FPGA 5 for configuring a logical circuit on the basis of configuration information acquired from the host computer 1 through the bus 2, and an address register 6 for storing an address which is common to that of other dedicated computer. When the host computer 1 provides the configuration information to the bus 2 with a common address, the plurality of dedicated computers 3 simultaneously acquire the configuration information of the common address from the bus 2, and configure the logical circuit of the FPGA 5. COPYRIGHT: (C)2005,JPO&NCIPI
申请公布号 JP2005190070(A) 申请公布日期 2005.07.14
申请号 JP20030429175 申请日期 2003.12.25
申请人 NEC CORP 发明人 SHOTANI TOMOYUKI;SHIMADA TOSHIRO
分类号 G06F15/80;(IPC1-7):G06F15/80 主分类号 G06F15/80
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