发明名称 Calibration device for a phased locked loop synthesiser
摘要 A calibration device for a phase locked loop arranged to generate an output frequency based upon a first frequency range of an input signal applied to a first input and a second frequency range of the input signal applied to a second input, the calibration phase locked loop synthesizer device comprising an estimator arranged to use a two dimensional estimation algorithm with a signal value indicative of a mismatch between the first input path and the second input path to determine an estimate of the mismatch to allow matching of the first input path and the second input path.
申请公布号 US2005151595(A1) 申请公布日期 2005.07.14
申请号 US20040991811 申请日期 2004.11.18
申请人 PRATT PATRICK J.;MILYARD MICHAEL A.;NIGRA LOUIS M.;SCHWARTZ DANIEL B. 发明人 PRATT PATRICK J.;MILYARD MICHAEL A.;NIGRA LOUIS M.;SCHWARTZ DANIEL B.
分类号 H03C3/09;H03L7/00;H03L7/099;H03L7/18;(IPC1-7):H03L7/00 主分类号 H03C3/09
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