发明名称 Switch for bus optimization
摘要 There is disclosed a bus optimization technique. Pursuant to the bus optimization technique, the output buffer and output logic are removed from port units of a switch and are included with a control matrix in the switch. Data units received in a first port unit of a plurality of port units are provided to a control matrix. The control matrix evaluates when to send the data unit to a second port unit. No output decisions are made in the second port unit.
申请公布号 US2005154804(A1) 申请公布日期 2005.07.14
申请号 US20050031420 申请日期 2005.01.07
申请人 STEWART HEATH;HAYWOOD CHRIS;DE LA GARRIGUE MICHAEL;SHAIKLI NADIM;WONG KEN;VUONG BAO;REINER THOMAS;RAPPOPORT ADAM 发明人 STEWART HEATH;HAYWOOD CHRIS;DE LA GARRIGUE MICHAEL;SHAIKLI NADIM;WONG KEN;VUONG BAO;REINER THOMAS;RAPPOPORT ADAM
分类号 G06F3/00;G06F13/14;G06F13/40;(IPC1-7):G06F3/00 主分类号 G06F3/00
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