| 摘要 |
<p>An apparatus for synchronizing signals. For memory devices (30), such as SDRAMs, implementing a synchronization device (54) to synchronize one signal, such as an external clock signal with a second signal, such as a data signal, tuning elements (74) (96) (126) and (70) (100) (132) may be provided at various points in the signal path of the synchronization device (54). The tuning elements (74) (96) (126) and (70) (100) (132) are designed to be identical, such that a single design may be used to a signal mismatch that is produced in either direction, using a single design. The tuning elements (74) (96) (126) and (70) (100) (132) may be implemented to provide, uniformity in the access time through a range of conditions, such as drain voltages and temperatures.</p> |
