Circuit arrangement for generating a digital clock signal

摘要

The arrangement has a capacitance which is alternately charged and discharged via two FET transistors. The voltage present at the capacitance is fed to positive input (52) of a comparator (50). The output voltage of the comparator, representing a digital clock signal is fed back to the input of an inverter (40) for providing two switching thresholds and to the gate terminals of the FET transistors.