| 摘要 |
An integrated circuit is used to test a computer system containing a bus. The circuit comprises a processor core, a data request pipeline with an external bus interface and a validation functional unit block (FUB) 300. The validation block has a latch 310 connected to the external bus interface and a request library 320. When a transaction from the bus is latched, it is checked to see if it matches a trigger condition. If so, then a request is generated using the library and posted on the bus 130. The condition may be that the latched transaction is of a type held in a register 332. The new transaction may be selected from the library using an index register 334. The address of the new transaction may be generated from the address in the latched transaction. |
