发明名称 |
System and method for scheduling instructions to maximize outstanding prefetches and loads |
摘要 |
The present invention discloses a method and device for ordering memory operation instructions in an optimizing compiler. for a processor that can potentially enter a stall state if a memory queue is full. The method uses a dependency graph coupled with one or more memory queues. The dependency graph is used to show the dependency relationships between instructions in a program being compiled. After creating the dependency graph, the ready nodes are identified. Dependency graph nodes that correspond to memory operations may have the effect of adding an element to the memory queue or removing one or more elements from the memory queue. The ideal situation is to keep the memory queue as full as possible without exceeding the maximum desirable number of elements, by scheduling memory operations to maximize the parallelism of memory operations while avoiding stalls on the target processor.
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申请公布号 |
US6918111(B1) |
申请公布日期 |
2005.07.12 |
申请号 |
US20000679434 |
申请日期 |
2000.10.03 |
申请人 |
SUN MICROSYSTEMS, INC. |
发明人 |
DAMRON PETER C.;KOSCHE NICOLAI |
分类号 |
G06F9/45;(IPC1-7):G06F9/45 |
主分类号 |
G06F9/45 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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