| 摘要 |
An Analog-to-Digital-Converter (ADC) converts an analog signal to digital data. The ADC includes a modulator, a decimation filter, and a time dither clock reduction circuit. The modulator receives the analog signal and a feedback signal and, based there upon, produces a modulated signal at a modulator clock rate. The decimation filter couples to the modulator, receives the modulated signal, and decimates and filters the modulated signal to produce the digital data. The time dither clock reduction circuit receives the modulated signal and provides the feedback signal to the modulator. The time dither clock reduction circuit applies both clock reduction and time dithering to the modulated signal to produce the feedback signal. At each modulator clock cycle, the time dithering clock reduction circuit considers modulated signals for a dithering factor, N, previous modulator clock cycles and a modulated signal for a current modulator clock cycle. If at least one constraint is satisfied for the N previous modulator clock cycles, the time dithering clock reduction circuit is allowed to transition the feedback signal with the modulated signal. If not, the time dithering clock reduction circuit holds the prior value of the feedback signal. After a transition, a new dithering factor may be determined. The ADC may be contained in a wireless local area network (WLAN) transceiving integrated circuit that services voice communications in a WLAN with at least one other WLAN device.
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