发明名称 |
Method, architecture and circuitry for controlling pulse width in a phase and/or frequency detector |
摘要 |
An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to present a parallel output data signal in response to (i) a first clock signal and (ii) one or more serial data signals. The second circuit may be configured to present the one or more serial data signals and the first clock signal in response to (i) a second clock signal and (ii) a parallel input data signal.
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申请公布号 |
US6917661(B1) |
申请公布日期 |
2005.07.12 |
申请号 |
US19990404891 |
申请日期 |
1999.09.24 |
申请人 |
CYPRESS SEMICONDUCTOR CORP. |
发明人 |
SCOTT PAUL H.;RAZA S. BABAR |
分类号 |
H03K5/00;H03K5/13;H03L7/081;H03L7/091;H04L7/00;H04L7/033;(IPC1-7):H03D3/24 |
主分类号 |
H03K5/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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