发明名称 |
Semiconductor memory array of floating gate memory cells with buried bit-line and vertical word line transistor |
摘要 |
A self aligned method of forming a semiconductor memory array of floating gate memory cells in a semiconductor substrate, and an array formed thereby, whereby each memory cell includes a trench formed into a surface of a semiconductor substrate, spaced apart source and drain regions with a channel region formed therebetween. The drain region is formed underneath the trench, and the channel region includes a first portion that extends substantially vertically along a sidewall of the trench and a second portion that extends substantially horizontally along the surface of the substrate. An electrically conductive floating gate is formed over and insulated from at least a portion of the channel region and a portion of the source region. An electrically conductive control gate is formed having a first portion disposed in the trench and a second portion formed over but insulated from the floating gate.
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申请公布号 |
US6917069(B2) |
申请公布日期 |
2005.07.12 |
申请号 |
US20010982413 |
申请日期 |
2001.10.17 |
申请人 |
SILICON STORAGE TECHNOLOGY, INC. |
发明人 |
KIANIAN SOHRAB;WANG CHIH HSIN |
分类号 |
H01L21/8247;H01L27/115;H01L29/423;H01L29/788;(IPC1-7):H01L29/788 |
主分类号 |
H01L21/8247 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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