| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit having a clock distribution circuit reducing clock skew independently from temperature variation or voltage variation without requiring significant labor, and also to provide its fabricating process. <P>SOLUTION: In a clock distribution circuit 1 mounted on a semiconductor integrated circuit, a clock signal distribution path to the second buffer stage 20A of a second circuit block 20 having a smaller number of buffer stages is configured by utilizing a part of clock signal distribution path passing the first buffer stage 10A from the first selector 11 of a first circuit block 10 having a larger number of buffer stages. <P>COPYRIGHT: (C)2005,JPO&NCIPI</p> |
