发明名称 METHOD AND DEVICE FOR LAYOUT DESIGN OF SEMICONDUCTOR INTEGRATED CIRCUIT
摘要 PROBLEM TO BE SOLVED: To achieve characteristics of an analog circuit to suppress an external noise and to shorten a layout design period. SOLUTION: A layout design device has element characteristic information 1, circuit connection information 2, process information 3, layout information 4, an analog core and function block division means 5, an optimizing means 6 based on a floor plan, a function block synthesizing means 7, an analog core arranging means 8, a wiring means 9 of signal wiring, a wiring means 10 of power supply wiring, and layout data 11. COPYRIGHT: (C)2005,JPO&NCIPI
申请公布号 JP2005182572(A) 申请公布日期 2005.07.07
申请号 JP20030424217 申请日期 2003.12.22
申请人 TOSHIBA MICROELECTRONICS CORP;TOSHIBA CORP 发明人 HASEGAWA KENJI;KUWANA KIYOHISA
分类号 G06F17/50;H01L21/82;H01L21/822;H01L27/04;(IPC1-7):G06F17/50 主分类号 G06F17/50
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