| 发明名称 |
Damascene process for fabricating interconnect layers in an integrated circuit |
| 摘要 |
A damascene process using a doped and undoped oxide ILD is described. The selectivity between the carbon doped and carbon free oxide provides an etching stop between the ILD's in addition to providing mechanical strength to the structure.
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| 申请公布号 |
US2005148190(A1) |
申请公布日期 |
2005.07.07 |
| 申请号 |
US20030746420 |
申请日期 |
2003.12.24 |
| 申请人 |
DUBIN VALERY M.;HUSSEIN MAKAREM A.;BOHR MARK |
发明人 |
DUBIN VALERY M.;HUSSEIN MAKAREM A.;BOHR MARK |
| 分类号 |
H01L21/311;H01L21/316;H01L21/768;(IPC1-7):H01L21/311 |
主分类号 |
H01L21/311 |
| 代理机构 |
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代理人 |
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| 主权项 |
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| 地址 |
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