Negative differential resistance (NDR) memory device with reduced soft error rate

摘要

An active negative differential resistance element (an NDR FET) and a memory device (such as an SRAM) using such elements is disclosed. Soft error rate (SER) performance for NDR FETs and such memory devices are enhanced by adjusting a location of charge traps in a charge trapping layer that is responsible for effectuating an NDR behavior. Both an SER and a switching speed performance characteristic can be tailored by suitable placement of the charge traps.