| 摘要 |
A test scheme which includes a drive circuit connected to a plurality of IP cores (such as memory blocks, processors (i.e., ARM, MIPS, ZSP) or special types of IO's (i.e., Gigablaze, Hyperphi)). The drive circuit is configured to simultaneously send the same input stimuli to each of the IP cores. Outputs of the IP cores are run through a comparator, and the comparator is configured to identify when the outputs from the IP cores are not identical.
|
