发明名称 |
PILLAR CELL FLASH MEMORY TECHNOLOGY |
摘要 |
<p>An array of a pillar-type nonvolatile memory cells (803) has each memory cell isolated from adjacent memory cells by a trench (810). Each memory cell is formed by a stacking process layers on a substrate: tunnel oxide layer (815), polysilicon floating gate layer (819), ONO or oxide layer (822), polysilicon control gate layer (825). Many aspects of the process are self-aligned. An array of these memory cells will require less segmentation. Furthermore, the memory cell has enhanced programming characteristics because electrons are directed at a normal or nearly normal angle (843) to the floating gate (819).</p> |
申请公布号 |
WO2005062378(A1) |
申请公布日期 |
2005.07.07 |
申请号 |
WO2004US40324 |
申请日期 |
2004.12.01 |
申请人 |
SANDISK CORPORATION;MOKHLESI, NIMA;LUTZE, JEFFREY W. |
发明人 |
MOKHLESI, NIMA;LUTZE, JEFFREY W. |
分类号 |
G11C16/04;H01L21/336;H01L21/8247;H01L27/115;H01L29/423;(IPC1-7):H01L21/824 |
主分类号 |
G11C16/04 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|