| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide an execution core architecture that effectively and efficiently reduces the occurrence of bubbles in an execution pipeline without requiring a substantial increase in chip area. <P>SOLUTION: Instruction dispatch in a multithreaded microprocessor such as a graphics processor is not constrained by an order among the threads. An instruction is fetched into an instruction buffer that stores an instruction from each of the threads. A dispatch circuit determines which instruction in the buffer is ready to be executed, and issues the instruction that is ready for execution. An instruction from one thread may be issued prior to an instruction from another thread regardless of which instruction was fetched into the buffer first. When an instruction from a particular thread is issued, the fetch circuit fills the available buffer location by the subsequent instruction from the thread. <P>COPYRIGHT: (C)2005,JPO&NCIPI</p> |
