| 摘要 |
PROBLEM TO BE SOLVED: To accelerate the mean value arithmetic operation of two binary numbers by solving the problem wherein, in a mean value calculating circuit 970 with a parity predicting circuit, a path for calculating an addition result parity from input data and further calculating the parity of a mean value by using the calculated addition result parity, is turned into a delay critical path, and the performance of the mean value calculation processing is deteriorated. SOLUTION: A carry generating circuit 220 generates a carry by using the least significant bits X<00> and Y<00> of two input data X<15:00> and Y<15:00>, and an adder 210 adds data X<"0", 15:01> and Y<"0", 15:01> obtained by shifting each of the two input data by one bit to the right to a carry C' generated by the carry generating circuit 220. Also, the carry generating circuit 220 outputs a carry C'=X<00>+Y<00>("+" is a logical sum) when the mean value is calculated by rounding off, and outputs C'=X<00>&Y<00> when the mean value is calculated by disregarding fractions. COPYRIGHT: (C)2005,JPO&NCIPI
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