发明名称 COMMON BIAS CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide a common bias circuit which reduces offset fluctuations in bias voltage in the midpoint of a magnetoresistive element by an input leakage current of a differential current amplification circuit. SOLUTION: A midpoint potential VM of the magnetoresistive element (RMR) is set to be zero by allowing an input leakage current of the differential current amplification circuit (IB1), an input leakage current of a pseudo-differential amplification circuit (IB2), a first resistance (R1), a second resistance (R2), a third resistance (R3), and a fourth resistance (R4) to have the following relationships: R1=R2, R3=R4, and R3×IB1=2×R1×IB2. COPYRIGHT: (C)2005,JPO&NCIPI
申请公布号 JP2005181142(A) 申请公布日期 2005.07.07
申请号 JP20030423357 申请日期 2003.12.19
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 SAITO HIROSHI
分类号 G01R33/09;H03F3/34;H03F3/45;(IPC1-7):G01R33/09 主分类号 G01R33/09
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