Wafer-level testing apparatus

摘要

A semiconductor component configured for wafer-level testing includes a semiconductor die having at least one die contact electrically exposed for coupling with a redistribution circuit that electrically couples at least one die contact to an extended contact such as a bumped contact. A wafer-level redistribution circuit interconnects a plurality of dice and includes a redistribution circuit for coupling between a die contact on one of the dice and a corresponding bumped contact. The wafer-level redistribution circuit further includes a bus conductor traversing each of the plurality of dice for electrically coupling with at least another one of the plurality of dice. At least one other conductor couples the redistribution circuit to the bus conductor.