Design method and system for optimum performance in integrated circuits that use power management

摘要

The present invention provides a method ( 100 ) of designing a circuit. The method comprises specifying ( 105 ) a design parameter for memory transistors and logic transistors and selecting ( 110 ) a test retention-mode bias voltage for the memory transistors. The method further comprises determining ( 115 ) a first relationship of a retention-mode leakage current and the design parameter at the test retention-mode bias voltage and obtaining ( 120 ) a second relationship of an active-mode drive current and the design parameter. The first and second relationships are used ( 125 ) to assess whether there is a range of values of the design parameter where the retention-mode leakage current and the active-mode drive current are within a predefined circuit specification. The method also includes adjusting ( 130 ) the test retention-mode bias voltage and repeating the determining and the using if the retention-mode total leakage current or the active-mode drive current is outside of the predefined circuit specification.