| 摘要 |
PROBLEM TO BE SOLVED: To reduce a layout size by reducing the area of an inter-cell wiring region, and to shorten the development period of an IC/LSI. SOLUTION: A compaction device is provided with a memory part 1, a system part 2, an arithmetic part 3 and a display part 4. The memory part 1 is provided with a net list 11, a design condition 12, a model parameter 13, a cell shape 14 and a mask pattern 15. The net list 11 stores data showing the connection relation of layout elements configuring a cell. The design condition 12 stores design data such as a design reference. A model parameter 13 stores the data of the model parameter of elements and wiring. The cell shape 14 stores the data of the cell shape. A mask pattern 15 stores the mask pattern data posterior to compaction processing. COPYRIGHT: (C)2005,JPO&NCIPI
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