发明名称 |
LOW-POWER COMPILER-PROGRAMMABLE MEMORY WITH FAST ACCESS TIMING |
摘要 |
A low-power, compilable memory (100) uses a charging pulse technique to improve access times over other low-power memory implementations. The memory includes circuitry (106, 108) configured to discharge a plurality of bit lines during an inactive memory access period to reduce power consumption. The memory also includes other circuitry (112) that applies a charging pulse during an active memory access period on a select one of the plurality of bit lines in order to improve the memory access times. An automatic memory compiler adjusts a timing circuit (130) to control the duration of the charging pulse and the enabling of a sense amplifier circuit (124)during memory design. The memory compiler provides a programmable physical size of the memory and optimizes the access timing while ensuring reliable sensing. The compiler calculates timing for the timing circuit according to a mathematical formula that provides for highly accurate and predicable access time delays for multiple memory configurations. |
申请公布号 |
WO2005060465(A2) |
申请公布日期 |
2005.07.07 |
申请号 |
WO2004US38027 |
申请日期 |
2004.11.15 |
申请人 |
FREESCALE SEMICONDUCTOR, INC.;NICHOLES, JAMES, W. |
发明人 |
NICHOLES, JAMES, W. |
分类号 |
G06F17/50;G11C7/00;G11C7/06;G11C7/12;G11C7/22;G11C17/12 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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