| 摘要 |
<p>A semiconductor integrated circuit device (1) has a trace memory controller (10). This trace memory controller (10) records a non-maskarable interrupt request signal NM1 which is input via a system control terminal SP, a standby signal STBY, a reset signal RES, information from a program counter, an instruction register, a general-purpose register, and a flag register of a CPU (4), a software standby signal output from the CPU (4), and an internal power source voltage VCC supplied via the power terminal DP, thereby maintaining the state of various signals when the semiconductor integrated circuit device (1) malfunctions due to a noise or the like. When a malfunction occurs, various information stored in a trace memory 16 of the trace memory controller 10 are read out and the malfunction is analyzed.</p> |
