发明名称 Clock recovery circuit
摘要 In a clock recovery circuit for DTV using a VSB modulation method, if the frequency of the symbol clock is fs, since the frequency difference between the fs/2 component signal of the VSB signal and the pilot signal is constant at fs/2, it is possible accurately to detect the phase error from their differential signal. Furthermore there is no distortion of the clock signal frequency of the VSB signal, even when the symbol data is distorted by multi-pass distortion or the like, since clock signal regeneration is performed by frequency domain processing. By employing this type of principle and performing phase error detection for each symbol at a time, it is possible to ensure a high speed tracking performance for clock signal regeneration.
申请公布号 US6914945(B2) 申请公布日期 2005.07.05
申请号 US20010883174 申请日期 2001.06.19
申请人 MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. 发明人 KATO HISAYA;KANNO IPPEI;AZAKAMI HIROSHI
分类号 H04N5/06;H04J3/00;H04L7/00;H04L7/027;H04L27/06;H04N5/455;H04N7/26;(IPC1-7):H04L27/16 主分类号 H04N5/06
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