| 摘要 |
A circuit to operate a semiconductor integrated circuit memory device having memory cells in a deep power down mode. The power down circuit includes a transistor switch connected between an external voltage source and the device memory cells and peripheral circuits, a generator for providing a control voltage of a first level different from the value of the external voltage, and a multiplexer that receives as one input the control voltage and as a second input the external voltage. The multiplexer has a selected output of one of the control voltage and external voltage that is applied to a control electrode of the transistor switch. When deep power down mode operation is required, the multiplexer responds to a power down control flag signal to apply the external voltage to the transistor control electrode to turn off the transistor and block application of the external voltage to the memory cells and peripheral circuits. In normal operation, no power down control flag signal is produced and the multiplexer applies the control voltage of a first level to the transistor switch control electrode to cause the transistor to conduct and apply the external voltage to the device memory cells and peripheral circuits for normal operation.
|
