发明名称 |
Method and apparatus for reducing power consumption in a memory array with dynamic word line driver/decoders |
摘要 |
A memory array includes a storage unit with a number of sections and decoders coupled to respective ones of the sections for decoding an N-bit address signal and responsively asserting a signal on one of the word lines selected by the address signal. Local clock buffers are coupled to respective ones of the decoders for receiving a clock signal and an address signal including M most-significant bits of the N-bit address signal and generating respective timing signals. The decoders receive the timing signal from their respective local clock buffers. Each decoder is operable to alternately precharge and evaluate the N-bit address signal responsive to phases of the timing signal. Each local clock buffer is operable, responsive to a state of the M bits of the address signal, for selecting between holding its timing signal in a deasserted state and enabling its timing signal to follow the clock signal.
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申请公布号 |
US6914849(B2) |
申请公布日期 |
2005.07.05 |
申请号 |
US20030687238 |
申请日期 |
2003.10.16 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
CAO TAI ANH;CHU SAM GAT-SHANG;MCGILL IV JOSEPH J.;VADEN MICHAEL THOMAS |
分类号 |
G11C7/10;G11C7/22;G11C8/08;G11C8/18;(IPC1-7):G11C8/00 |
主分类号 |
G11C7/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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