| 摘要 |
There is provided a MRAM capable of reading at any timing information of memory cells at different addresses connected to the same bit line. Specifically, a memory cell of an address (AD 00 ) has MOS transistors (Q 1 , Q 2 ) connected in series and a magnetic tunnel resistive element (MR 00 ), which are disposed between bit lines (BL 0 a, BL 0 b). The gate electrodes of the MOS transistors (Q 1 , Q 2 ) are respectively connected to word lines (WL 0 a, WL 0 b). Memory lines (ML 0 , ML 1 ) are connected in common to a reference voltage source (VR 1 ) via N-channel MOS transistors (Q 3 , Q 31 ), and are respectively connected to current sources with a switch (S 1 , S 2 ). The bit lines (BL 0 a, BL 0 b, BL 1 a, BL 1 b) are respectively connected to inputs of buffers with a switch (B 1 to B 4 ), and their outputs are supplied to the corresponding sense amplifier (SA 1 ). |
