发明名称 |
On-chip frequency degradation compensation |
摘要 |
Embodiments of the invention include a trio of reliability oscillators. In one embodiment, an on-chip frequency compensation circuit includes a selectively enabled reliability oscillator to generate a reference oscillating signal, a clocked reliability oscillator to generate an AC degraded oscillating signal, and a static reliability oscillator to generate a DC bias degraded oscillating signal. A compare circuit coupled to the reliability oscillators compares the oscillating signals and generates a frequency compensation signal if the comparison determines that there is frequency degradation greater than a predetermined threshold.
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申请公布号 |
US2005140418(A1) |
申请公布日期 |
2005.06.30 |
申请号 |
US20030751132 |
申请日期 |
2003.12.31 |
申请人 |
MUNIANDY RAVISANGAR;TAYLOR GREGORY F.;AMINZADEH PAYMAN |
发明人 |
MUNIANDY RAVISANGAR;TAYLOR GREGORY F.;AMINZADEH PAYMAN |
分类号 |
G06F1/04;(IPC1-7):G06F1/04 |
主分类号 |
G06F1/04 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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