发明名称 Hierarchical virtual model of a cache hierarchy in a multiprocessor system
摘要 The cache coherency protocol described herein can be used to maintain a virtual model of a system, where the virtual model does not change as the system configuration changes. In general, the virtual model is based on the assumption that each node in the system can directly communicate with some number of other nodes in the system. In one embodiment, for each cache line, the address of the cache line is used to designate a node as the "home" node and all other nodes as "peer" nodes. The protocol specifies one set of messages for communication with the line's home node and another set of messages for communication with the line's peer nodes.
申请公布号 US2005144400(A1) 申请公布日期 2005.06.30
申请号 US20050069848 申请日期 2005.02.28
申请人 HUM HERBERT H.;GOODMAN JAMES R. 发明人 HUM HERBERT H.;GOODMAN JAMES R.
分类号 G06F12/08;(IPC1-7):G06F12/00 主分类号 G06F12/08
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