| 摘要 |
An internal clock doubler comprises a clock delay unit, an edge detecting unit and an output driver. The clock delay unit delays a clock signal for a predetermined delay time and outputs a delay clock signal. The edge detecting unit detects rising and falling edges of the clock signal in response to the delay clock signal and outputs a rising pulse signal and a falling pulse signal. The output driver outputs a double clock signal toggled at every rising edge and every falling edge of the clock signal in response to the rising pulse signal and the falling pulse signal. As a result, since a double clock signal having double frequency of an internal clock signal is generated without external input of an additional clock signal through an additional pad, a stable high-speed test can be performed on a semiconductor memory device.
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