Address space, bus system, memory controller and device system

摘要

Memory capacity requirements in systems-on-chip have led to the use of DRAM-based memory devices. A property of these devices is the burst-oriented access of data. These bursts can be considered as successive non-overlapping blocks of data in the memory that can only be accessed as an entity. Therefore, when a data entity is accessed, it is always aligned with a grid that has the same granularity as the data entities. The size of the data entities is determined by the length of the burst and the width of the memory bus. A way to refine the alignment grid although the amount of bytes per burst remains equal is proposed. A solution for a memory controller is presented that features separate address busses for several parallel memory devices instead of a shared address bus. Due to the refined alignment grid, the amount of transfer overhead can be reduced significantly. The drawback of the invention for off-chip memory devices is the increase in the system costs and the power dissipation. However, for embedded DRAM the additional costs are limited.