| 摘要 |
<P>PROBLEM TO BE SOLVED: To achieve a low spurious delta sigma fractional frequency division PLL synthesizer. <P>SOLUTION: First and second L-value accumulators 31, 30 are provided; the difference between overflow signals 16, 17 of the first and second L-value accumulators 31, 30 is obtained by an adder 29; and the division ratio of a variable divider 2 for allowing the division ratio to be changed to M, M+1, and M-1 is changed by the output signal of the adder 29, thus shifting a spurious frequency generated by the operational noise of the first and second L-value accumulators 31, 30 to a frequency component that is higher than a prior art for eliminating by a loop filter (low-pass filter) 5. <P>COPYRIGHT: (C)2005,JPO&NCIPI |
