| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To allow reducing a cell area of a non-volatile memory composed of a single layer polysilicon gate and to enable operation of the memory in a superlow power consumption. <P>SOLUTION: A reverse bias voltage, such as -5V, is applied to a p-type impurity area 11 positioned on a substrate surface of an n-type well 4 of a lower portion of a floating gate 6 through a gate oxide film 5 and is applied to a junction constructed by the n-type well 4, and hot electrons produced from a tunnel phenomenon between bands is implanted into the floating gate 6, then, the write is carried out. It is designed that the write time is about 10μs and the leakage current of the junction in writing is approximate 100 ns, therefore, the energy necessary for writing is reduced up to 5 pJ, that is, reduced to 1/100 or less, compared with a writing energy used in implantation of channel hot electron of the customary stacked gate type memory. <P>COPYRIGHT: (C)2005,JPO&NCIPI</p> |
