发明名称 MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE
摘要 PROBLEM TO BE SOLVED: To provide a manufacturing method of semiconductor devices capable of suppressing adverse effect on element characteristics and forming an extension region wherein a joining depth is comparatively shallow. SOLUTION: A liner insulation film 18 covers a side circumferential wall of a gate electrode 17a and the end of a gate insulation film to suppress damages to the gate insulation film and a semiconductor substrate caused in the manufacturing process, and a source and drain region 20 is formed and thereafter the extension region 21 is formed to make the joining depth of the extension region 21 comparatively shallow. COPYRIGHT: (C)2005,JPO&NCIPI
申请公布号 JP2005175132(A) 申请公布日期 2005.06.30
申请号 JP20030411760 申请日期 2003.12.10
申请人 TOSHIBA CORP 发明人 IINUMA TOSHIHIKO
分类号 H01L21/28;H01L21/265;H01L21/336;H01L21/8238;H01L27/092;H01L29/417;H01L29/78;(IPC1-7):H01L21/336;H01L21/823 主分类号 H01L21/28
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