| 摘要 |
PROBLEM TO BE SOLVED: To provide a clock frequency multiplying circuit device enabling to further improve stability. SOLUTION: A control circuit is configured so that the operation sequence of a DCO and a counter/data latch circuit are controlled according to each state shifted by a state machine. The state machine is configured to change the shift time of the states according to a processing time necessary for each state, and as for the state (3) for which a long processing time is required, the period is made long, and as for the states (1), (2), (4) to (8) whose processing time is short, the period is made short. COPYRIGHT: (C)2005,JPO&NCIPI
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