发明名称 A PHASE LOCKED LOOP THAT SETS GAIN AUTOMATICALLY
摘要 There is provided a phase locked loop, PLL, that sets gain automatically. The PLL comprises a frequency discriminator for providing a first signal that represents the difference between a first frequency and a second frequency. The PLL also comprises a comparator coupled to the frequency discriminator for receiving the first signal and providing a second signal based on information from the first signal. The second signal is representative of a gain setting for the phase locked loop to set.
申请公布号 WO2005060103(A2) 申请公布日期 2005.06.30
申请号 WO2004US42040 申请日期 2004.12.13
申请人 QUALCOMM INCORPORATED;HARRIS, MARK V. 发明人 SMITH, ALAN, ANDREW DI;HARRIS, MARK V.
分类号 H03L7/00;H03L7/093;H03L7/107;H03L7/113;H03L7/18 主分类号 H03L7/00
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