| 摘要 |
PROBLEM TO BE SOLVED: To enlarge a data reading potential difference, to reduce current consumption and to perform high-speed operation in a ferroelectric memory device. SOLUTION: Each of paired bit lines BL0, BL1 for reading data of memory cells 11-14 comprises a bit line capacitance regulation circuit 21 comprised of a first regulation capacitor CA0 for regulating a capacitance value of the bit line BL0, a second regulation capacitor CA1 for regulating a capacitance value of the bit line BL1, a first switch transistor TA0 for controlling electrical connection between the bit line BL0 and the first regulation capacitor CA0, and a second switch transistor TA1 for controlling electrical connection between the bit line BL1 and the second regulation capacitor CA1. COPYRIGHT: (C)2005,JPO&NCIPI
|
