发明名称 Processor including branch prediction mechanism for far jump and far call instructions
摘要 A method and apparatus are provided for processing far jump-call branch instructions to increase the efficiency of a processor pipeline. The processor includes a far jump-call target buffer which stores the default address/operand size corresponding to each of a plurality of previously executed far jump-call instructions. When a far jump-call instruction is encountered, it is speculatively executed using the corresponding default address/operand size for that instruction as stored in the far jump-call target buffer. This speculative far jump-call instruction is executed and resolved thus determining the actual address/operand size. If the actual address/operand size matches the speculative default address/operand size then the speculation was correct and processing continues. However, if there is no match, then the speculation was wrong and the pipeline is flushed.
申请公布号 US2005144427(A1) 申请公布日期 2005.06.30
申请号 US20020279205 申请日期 2002.10.22
申请人 IP-FIRST LLC 发明人 COL GERARD M.;MCDONALD THOMAS C.
分类号 G06F9/30;G06F9/32;G06F9/38;(IPC1-7):G06F9/30 主分类号 G06F9/30
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