Fast reading, low power consumption memory device and reading method thereof

摘要

A memory device having a reading configuration and including a plurality of memory cells (3), arranged in rows and columns, memory cells (3) arranged on the same column having respective first terminals (3a) connected to a same bit line (12) and memory cells (3) arranged on the same row having respective second terminals (3b) selectively connectable to a same word line (13); a supply line (9) providing a supply voltage (VDD); a column addressing circuit (4) and a row addressing circuit (5) for respectively addressing a bit line (12) and a word line (13) corresponding to a memory cell (3) selected for reading in the reading configuration. The column addressing circuit (4) is configured to bias the addressed bit line (12) corresponding to the selected memory cell (3) substantially at the supply voltage (VDD) in the reading configuration. A row driving circuit (6) biases the addressed word line (13) corresponding to the selected memory cell (3) at a non-zero word line read voltage (VWL), so that a predetermined cell voltage (VCELL), lower than a phase change voltage (VPHC), is applied between the first terminal (3a) and the second terminal (3b) of the selected memory cell (3) in the reading configuration.