| 摘要 |
A cue delay circuit for an ink jet printing system includes a state machine with sequenced logic circuits that generate buffered control signals; a counter that counts one of the buffered control signals to form a read address; and an adder that combines the read address to the cue delay value to generate a write address. A comparator compares the cue delay value to the read address to determine if the read address is greater than the cue delay value. A multiplexer receives the read and write address and one of the buffered control signals and forms a multiplexer output. The system includes a gate circuit that receives the latched comparator output and the RAM output signal forming a gated cue signal; and a logic circuit that sends a signal to the printing system.
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