| 摘要 |
A method, program product and computer system for hardware design and simulation thereof. In particular, the schematic description of a respective hardware macro is analyzed during the design of macros, and arrays. A path is traced in the schematic of said macro from a start point to an end point along a given hierarchy, collecting the relevant information of each cell found in the schematic being relevant for timing analysis of the macro, resolving the hierarchy structure of cells in the schematic in order to gain information about the selected path, and outputting information in a form which allows comparing, for example, a representation to be used for exact timing verification, a so called cross-section, with the macro schematic.
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