发明名称 Phase locked loop for phase or frequency modulation application, has phase comparator activating measurement signal during measurement time interval that is generated at duration defined by cycle count of high frequency signal
摘要 <p>The loop has a phase comparator (32) activating a phase difference measurement signal during a measurement time interval, when an active face of a reference signal falls inside the time interval, so that the signal includes pulses. The time interval is generated in response to an active face of the divided frequency signal, at a duration defined by cycle count of high frequency signal. One of the pulses is present between start of the measurement time interval and the active face of the reference signal. Another pulse is present between the active face of the reference signal and end of the time interval.</p>
申请公布号 FR2864377(A1) 申请公布日期 2005.06.24
申请号 FR20030014921 申请日期 2003.12.18
申请人 EADS TELECOM 发明人 ROBBE MICHEL;AISSA SAMI
分类号 H03D13/00;H03L7/085;H03L7/089;H03L7/191;(IPC1-7):H03L7/089 主分类号 H03D13/00
代理机构 代理人
主权项
地址