Dynamic random access memory for manufacturing e.g. system on chip, has state machine coupled to cache memories to allow simultaneous read and write access to memory plan, and error correction circuit to modify and write words in same page

摘要

The memory has a memory plan (2) with an array of memory cells arranged in rows and columns. Two cache memories (5, 6) allow alternative reading of words from a page of the memory and writing of new words in the page. A state machine (105) coupled to the cache memories allow simultaneous read and write access to the plan. An error correction circuit (110) allows reading, modification and writing of the words within the same page. An independent claim is also included for a method of controlling a dynamic random access memory (DRAM).