发明名称 |
Technique for generating output states in a security algorithm |
摘要 |
An architecture to perform a hash algorithm. Embodiments of the invention relate to the use of processor architecture logic to implement an addition operation of initial state information to intermediate state information as required by hash algorithms while reducing the contribution of the addition operation to the critical path of the algorithm's performance within the processor architecture.
|
申请公布号 |
US2005135604(A1) |
申请公布日期 |
2005.06.23 |
申请号 |
US20030745238 |
申请日期 |
2003.12.22 |
申请人 |
FEGHALI WAJDI K.;WOLRICH GILBERT M.;ADILETTA MATTHEW J.;BURRES BRAD A. |
发明人 |
FEGHALI WAJDI K.;WOLRICH GILBERT M.;ADILETTA MATTHEW J.;BURRES BRAD A. |
分类号 |
G06F7/507;G06F7/509;H04L9/32;(IPC1-7):H04L9/00;G06F7/38 |
主分类号 |
G06F7/507 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|