发明名称 Inter-process communication mechanism
摘要 A data processing apparatus comprises at least one source processor core ( 110 ), at least two destination processor cores ( 120 ), a message handler ( 130 ) and a bus arrangement ( 150 ) providing a data communication path between the source core, the destination cores and the message handler. The message handler ( 130 ) has plurality of message-handling modules ( 132 - 1 to 132 - 3 ). At least one of the message-handling modules has a message receipt indicator that is modifiable by each of the destination processor cores to indicate that a message has been received at its destination. This message-handling module also has a transmission completion detector operable to detect, in dependence upon a message receipt indicator value that a message has been received by all of the at least two destination processor cores and to initiate transmission of an acknowledgement signal to the source processor core.
申请公布号 US2005138249(A1) 申请公布日期 2005.06.23
申请号 US20040885240 申请日期 2004.07.07
申请人 GALBRAITH MARK J.;FEARNHAMM HARRY S.T.;SMITH NICHOLAS E.;MATHEWSON BRUCE J. 发明人 GALBRAITH MARK J.;FEARNHAMM HARRY S.T.;SMITH NICHOLAS E.;MATHEWSON BRUCE J.
分类号 G06F15/167;G06F11/30;G06F13/00;G06F15/163;G06F15/17;G06F15/80;(IPC1-7):G06F13/00 主分类号 G06F15/167
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