A synchronization circuit for re-synchronizing data from an input clock to an output clock is presented. The first transparent latch receives data synchronized to an input clock. A second transparent latch receives data from the first transparent latch and outputs data dependent on a delayed output clock which is the output clock delayed by an insertion delay. An output latch receives data from the second transparent latch and synchronizes data to the output clock.
申请公布号
WO2004059471(A3)
申请公布日期
2005.06.23
申请号
WO2003US40237
申请日期
2003.12.17
申请人
MOSAID TECHNOLOGIES, INC.;ROTH, ALAN;BECCA, OSWALD;OVALLE, PEDRO